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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS83905
LOW SKEW, 1:6 CRYSTAL INTERFACE-TOLVCMOS / LVTTL FANOUT BUFFER
FEATURES
* 6 LVCMOS / LVTTL outputs * Crystal oscillator interface * Output frequency range: 10MHz to 50MHz * Crystal input frequency range: 10MHz to 50MHz * Output skew: 10ps (typical) * 5V tolerant enable inputs * Synchronous output enables * Operating supply modes: Full 3.3V, 2.5V and 1.8V, mixed 3.3Vcore/2.5V or1.8V operating supply, and mixed 2.5V core/1.8V operating supply * 0C to 70C ambient operating temperature * Lead-Free package fully RoHS compliant * Pin compatible to MPC905 * Industrial version available upon request
GENERAL DESCRIPTION
The ICS83905 is a low skew, 1-to-6 LVCMOS / LVTTL Fanout Buffer and a member of the HiPerClockSTM HiPerClockSTM family of High Performance Clock Solutions from ICS. The ICS83905 single ended clock input accepts LVCMOS or LVTTL input levels. The low impedance LVCMOS/LVTTL outputs are designed to drive 50 series or parallel terminated transmission lines. The effective fanout can be increased from 6 to 12 by utilizing the ability of the outputs to drive two series terminated lines.
ICS
The ICS83905 is characterized at full 3.3V, 2.5V, and 1.8V, mixed 3.3V/2.5V, 3.3V/1.8V and 2.5V/1.8V output operating supply mode. Guaranteed output and part-to-part skew characteristics along with the 1.8V output capabilities makes the ICS83905 ideal for high performance, single ended applications that also require a limited output voltage.
BLOCK DIAGRAM
PIN ASSIGNMENT
BCLK0 XTAL_OUT ENABLE 2 GND BCLK0 VDDo BCLK1 GND BCLK2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 XTAL_IN ENABLE 1 BCLK5 VDDO BCLK4 GND BCLK3 VDD
BCLK1 XTAL_IN BCLK2
XTAL_OUT
ICS83905
BCLK3
BCLK4 ENABLE 1
16-Lead SOIC 3.9mm x 9.9mm x 1.38mm body package M Pacakge Top View
SYNCHRONIZE
BCLK5
ICS83905
16-Lead TSSOP 4.4mm x 3.0mm x 0.92mm body package G Pacakge Top View
XTAL_OUT ENABLE2 ENABLE1 XTAL_IN
ENABLE 2
SYNCHRONIZE
GND GND BCLK0 VDDO BCLK1
1 2 3
20 19 18 17 16 ICS83905 15
nc
BCLK5 VDDO BCLK4 GND GND
20-Lead VFQFN 14 4mm x 4mm x 0.9mm body package 13 4 K Package 12
5 6
GND
Top View
7
GND
11
BCLK3
8
BCLK2
9 10
VDD
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
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1
REV. A JANUARY 20, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS83905
LOW SKEW, 1:6 CRYSTAL INTERFACE-TOLVCMOS / LVTTL FANOUT BUFFER
Type Description Cr ystal oscillator interface. XTAL_OUT is the output. Cr ystal oscillator interface. XTAL_IN is the input. Output enable. LVCMOS / LVTTL interface levels. Clock outputs. LVCMOS / LVTTL interface levels. Power supply ground. Core supply pin. Output supply pin. No connect.
TABLE 1. PIN DESCRIPTIONS
Name XTAL_OUT XTAL_IN ENABLE 1, ENABLE2 BCLK0, BCLK1, BCLK2, BCLK3, BCLK4, BCLK5 GND VDD VDDO n/c Input Input Output Power Power Power Unused Output
TABLE 2. PIN CHARACTERISTICS
Symbol CIN C PD Parameter Input Capacitance Power Dissipation Capacitance (per output) VDDO = 3.465V VDDO = 2.625V VDDO = 2V VDDO = 3.3V 5% ROUT Output Impedance VDDO = 2.5V 5% VDDO = 1.8V 0.2V 5 7 7 10 Test Conditions Minimum Typical 4 19 18 16 12 Maximum Units pF pF pF pF
TABLE 3. OUTPUT ENABLE
Control Inputs ENABLE 1 0 0 1 1
AND
CLOCK ENABLE FUNCTION TABLE
Outputs BCLK0:BCLK4 LOW LOW Toggling Toggling BCLK5 LOW Toggling LOW Toggling
ENABLE 2 0 1 0 1
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REV. A JANUARY 20, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS83905
LOW SKEW, 1:6 CRYSTAL INTERFACE-TOLVCMOS / LVTTL FANOUT BUFFER
4.6V -0.5V to VDD + 0.5 V -0.5V to VDDO + 0.5V 78.8C/W (0 mps) 89C/W (0 lfpm) 38.5C/W (0 mps) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Character-
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, VO Package Thermal Impedance, JA 16 Lead SOIC package 16 Lead TSSOP package 20 Lead VFQFN package Storage Temperature, TSTG
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V5%, TA = 0C TO 70C
Symbol VDD VDDO IDD IDDO Parameter Core Supply Voltage Output Supply Voltage Power Supply Current Output Supply Current Test Conditions Minimum 3.135 3.135 Typical 3.3 3.3 TBD TBD Maximum 3.465 3.465 Units V V A A
TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 2.5V5%, TA = 0C TO 70C
Symbol VDD VDDO IDD IDDO Parameter Core Supply Voltage Output Supply Voltage Power Supply Current Output Supply Current Test Conditions Minimum 2.375 2.375 Typical 2.5 2.5 TBD TBD Maximum 2.625 2.625 Units V V A A
TABLE 4C. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 1.8V0.2V, TA = 0C TO 70C
Symbol VDD VDDO IDD IDDO Parameter Core Supply Voltage Output Supply Voltage Power Supply Current Output Supply Current Test Conditions Minimum 1.6 1.6 Typical 1.8 1.8 TBD TBD Maximum 2.0 2.0 Units V V A A
TABLE 4D. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 2.5V5%, TA = 0C TO 70C
Symbol VDD VDDO IDD IDDO Parameter Core Supply Voltage Output Supply Voltage Power Supply Current Output Supply Current Test Conditions Minimum 3.135 2.375 Typical 3.3 2.5 TBD TBD Maximum 3.465 2.625 Units V V A A
83905AM
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3
REV. A JANUARY 20, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS83905
LOW SKEW, 1:6 CRYSTAL INTERFACE-TOLVCMOS / LVTTL FANOUT BUFFER
Test Conditions Minimum 3.135 1.6 Typical 3.3 1.8 TBD TBD Maximum 3.465 2.0 Units V V A A
TABLE 4E. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 1.8V0.2V, TA = 0C TO 70C
Symbol VDD VDDO IDD IDDO Parameter Core Supply Voltage Output Supply Voltage Power Supply Current Output Supply Current
TABLE 4F. POWER SUPPLY DC CHARACTERISTICS, VDD = 2.5V5%, VDDO = 1.8V0.2V, TA = 0C TO 70C
Symbol VDD VDDO IDD IDDO Parameter Core Supply Voltage Output Supply Voltage Power Supply Current Output Supply Current Test Conditions Minimum 2.375 1.6 Typical 2.5 1.8 TBD TBD Maximum 2.625 2.0 Units V V A A
TABLE 4G. LVCMOS/LVTTL DC CHARACTERISTICS, TA = 0C TO 70C
Symbol VIH Parameter Input High Voltage ENABLE1, ENABLE2 Test Conditions VDD = 3.3V 5% VDD = 2.5V 5% VDD = 1.8V 0.2V VIL Input Low Voltage ENABLE1, ENABLE2 VDD = 3.3V 5% VDD = 2.5V 5% VDD = 1.8V 0.2V VDDO = 3.3V 5%; NOTE 1 VOH Output High Voltage VDDO = 2.5V 5%; IOH = -1mA VDDO = 2.5V 5%; NOTE 1 VDDO = 1.8V 0.2V; NOTE 1 VDDO = 3.3V 5%; NOTE 1 VOL Output Low Voltage VDDO = 2.5V 5%; IOL = 1mA VDDO = 2.5V 5%; NOTE 1 VDDO = 1.8V 0.2V; NOTE 1 Minimum 2 1.7 0.65*VDD -0.3 -0.3 -0.3 2.6 2 1.8 VDD - 0.3 0.5 0.4 0.45 0.35 Typical Maximum VDD + 0.3 VDD + 0.3 VDD + 0.3 1.3 0.7 0.35*VDD Units V V V V V V V V V V V V V V
NOTE 1: Outputs terminated with 50 to VDDO/2. See Parameter Measurement section, "Load Test Circuit" diagrams.
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REV. A JANUARY 20, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS83905
LOW SKEW, 1:6 CRYSTAL INTERFACE-TOLVCMOS / LVTTL FANOUT BUFFER
Test Conditions Using External Crystal Using External Clock Source HIGH (above 2V); NOTE 1 Minimum Typical Maximum Units 10 DC 0.5T T = Periods 0.5T 0.5T 0.5T T = desired Period TBD 10 20% to 80% E NA B LE 1 E NA B LE 2 500 TBD TBD TBD TBD TBD TBD ps ps ms ms ms ms db 50 100 MHz MHz
TABLE 5A. AC CHARACTERISTICS, VDD = VDDO = 3.3V5%, TA = 0C TO 70C
Symbol Parameter fMAX Output Frequency
t PW
Output Pulse Width
LOW (below 0.8V), NOTE 2 HIGH (above 2V); NOTE 1 LOW (below 0.8V), NOTE 2
tPER
Output Period Output Skew; NOTE 3, 5 Output Rise/Fall Time Output Enable Time; NOTE 4
tsk(o)
tR/tF
t EN tDIS
A OSC Phase
Output Disable Time; ENABLE 1 NOTE 4 ENABLE 2 XTAL_IN to XTAL_OUT Oscillator Gain Loop Phase Shift Modulo 360+
All parameters measured at fMAX unless noted otherwise. NOTE 1: Assuming input duty cycle specs from Recommended Operating Conditons table are met. NOTE 2: Assuming external crystal or 50% duty cycle external reference is used. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 4: These parameters are guaranteed by characterization. Not tested in production. NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 5B. AC CHARACTERISTICS, VDD = VDDO = 2.5V5%, TA = 0C TO 70C
Symbol Parameter fMAX odc t PER Output Frequency Output Duty Cycle Output Period Output Skew; NOTE 3, 5 Output Rise/Fall Time Output Enable Time; ENABLE 1 NOTE 4 ENABLE 2 Output Disable Time; ENABLE 1 NOTE 4 ENABLE 2 XTAL_IN to XTAL_OUT Oscillator Gain Loop Phase Shift Modulo 360+ 20% to 80% Using External Crystal Using External Clock Source Test Conditions Minimum Typical Maximum Units 10 DC 50 TBD 10 500 TBD TBD TBD TBD TBD TBD ps ps ms ms ms ms db 50 100 MHz MHz %
tsk(o)
tR/tF
t EN tDIS
A OSC Phase
See notes from Table 5A.
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83905AM
REV. A JANUARY 20, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS83905
LOW SKEW, 1:6 CRYSTAL INTERFACE-TOLVCMOS / LVTTL FANOUT BUFFER
Test Conditions Using External Crystal Using External Clock Source Minimum Typical Maximum Units 10 DC 50 TBD 10 20% to 80% 550 TBD TBD TBD TBD TBD TBD ps ps ms ms ms ms db 50 100 MHz MHz %
TABLE 5C. AC CHARACTERISTICS, VDD = VDDO = 1.8V0.2V, TA = 0C TO 70C
Symbol Parameter fMAX odc tPER Output Frequency Output Duty Cycle Output Period Output Skew; NOTE 3, 5 Output Rise/Fall Time Output Enable Time; ENABLE 1 NOTE 4 ENABLE 2 Output Disable Time; ENABLE 1 NOTE 4 E NA B LE 2 XTAL_IN to XTAL_OUT Oscillator Gain Loop Phase Shift Modulo 360+
tsk(o)
tR/tF
t EN tDIS
A OSC Phase
See notes from Table 5A.
TABLE 5D. AC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 2.5V5%, TA = 0C TO 70C
Symbol Parameter fMAX odc t PER Output Frequency Output Duty Cycle Output Period Output Skew; NOTE 3, 5 Output Rise/Fall Time Output Enable Time; ENABLE 1 NOTE 4 ENABLE 2 Output Disable Time; ENABLE 1 NOTE 4 ENABLE 2 XTAL_IN to XTAL_OUT Oscillator Gain Loop Phase Shift Modulo 360+ 20% to 80% Using External Crystal Using External Clock Source Test Conditions Minimum Typical Maximum Units 10 DC 50 TBD 10 500 TBD TBD TBD TBD TBD TBD ps ps ms ms ms ms db 50 100 MHz MHz %
tsk(o)
tR/tF
t EN tDIS
A OSC Phase
See notes from Table 5A.
83905AM
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6
REV. A JANUARY 20, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS83905
LOW SKEW, 1:6 CRYSTAL INTERFACE-TOLVCMOS / LVTTL FANOUT BUFFER
Test Conditions Using External Crystal Using External Clock Source Minimum Typical Maximum Units 10 DC 50 TBD 10 20% to 80% 550 TBD TBD TBD TBD TBD TBD ps ps ms ms ms ms db 50 100 MHz MHz %
TABLE 5E. AC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 1.8V0.2V, TA = 0C TO 70C
Symbol Parameter fMAX tPW tPER Output Frequency Output Pulse Width Output Period Output Skew; NOTE 3, 5 Output Rise/Fall Time Output Enable Time; ENABLE 1 NOTE 4 ENABLE 2 Output Disable Time; ENABLE 1 NOTE 4 E NA B LE 2 XTAL_IN to XTAL_OUT Oscillator Gain Loop Phase Shift Modulo 360+
tsk(o)
tR/tF
t EN tDIS
A OSC Phase
See notes from Table 5A.
TABLE 5F. AC CHARACTERISTICS, VDD = 2.5V5%, VDDO = 1.8V0.2V, TA = 0C TO 70C
Symbol Parameter fMAX odc tPER Output Frequency Output Duty Cycle Output Period Output Skew; NOTE 3, 5 Output Rise/Fall Time Output Enable Time; NOTE 4 Output Disable Time; NOTE 4 ENABLE 1 E NA B LE 2 ENABLE 1 ENABLE 2 20% to 80% Using External Crystal Using External Clock Source Test Conditions Minimum Typical Maximum Units 10 DC 50 TBD 10 550 TBD TBD TBD TBD TBD TBD ps ps ms ms ms ms db 50 100 MHz MHz %
tsk(o)
tR/tF
t EN tDIS
A OSC Phase
XTAL_IN to XTAL_OUT Oscillator Gain Loop Phase Shift Modulo 360+
See notes from Table 5A.
83905AM
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REV. A JANUARY 20, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS83905
LOW SKEW, 1:6 CRYSTAL INTERFACE-TOLVCMOS / LVTTL FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
1.65V5% 1.25V5%
VDD, VDDO
SCOPE
Qx
VDD, VDDO
SCOPE
Qx
LVCMOS
GND
LVCMOS
GND
-1.165V5%
-1.25V5%
3.3V
CORE/3.3V
OUTPUT LOAD AC TEST CIRCUIT
2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
0.9V0.1V
2.05V5%
1.25V5%
VDD, VDDO
SCOPE
Qx
VDD VDDO
SCOPE
Qx
LVCMOS
GND
LVCMOS
GND
-0.9V 0.1V
-1.25V5%
1.8V CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT
3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
2.40.9V
0.9V0.1V
1.6V0.025% 0.9V0.1V
V DD VDDO
SCOPE
Qx
V DD VDDO
SCOPE
Qx
LVCMOS
GND
LVCMOS
GND
-0.9V0.1V
-0.9V0.1V
3.3V CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT
83905AM
2.5 CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT
REV. A JANUARY 20, 2005
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS83905
LOW SKEW, 1:6 CRYSTAL INTERFACE-TOLVCMOS / LVTTL FANOUT BUFFER
V
V
2
DD
DDO
Qx
BCLKx
Pulse Width t
V
DDO
2
PERIOD
Qy
2 tsk(o)
odc =
t PW t PERIOD
OUTPUT SKEW
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
80% 20% tR
80% 20% tF
Clock Outputs
OUTPUT RISE/FALL TIME
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REV. A JANUARY 20, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS83905
LOW SKEW, 1:6 CRYSTAL INTERFACE-TOLVCMOS / LVTTL FANOUT BUFFER APPLICATION INFORMATION
CRYSTAL INPUT INTERFACE, FUNDAMENTAL
Figure 1A shows an example of ICS83905 crystal interface with parallel resonance crystal using fundamental frequency. The C1, C2 and R1 values are suggested for the best frequency accuracy ppm. The optimum C1 and C2 values can be adjusted to improve the frequency accuracy for stray capacitance of different board layout.
XTAL_IN
C1 10p
X1
R1
XTAL_OUT
C2 16p
100
FIGURE 1A. CRYSTAL OSCILLATOR INTERFACE, (FUNDAMENTAL)
CRYSTAL INPUT INTERFACE, 3RD OVERTONE
Figure 1B shows an example of ICS83905 crystal interface with parallel resonance crystal using 3rd overtone frequency. The C1, C2 values are suggested for the best frequency accuracy ppm.
The optimum C1 and C2 values can be adjusted to improve the frequency accuracy for stray capacitance of different board layout. The C3 and L1 can be calculated from the given equation.
XTAL_IN
C1 10p
X1
F _ fund =
1 2 L1 * C 3
XTAL_OUT
C2 16p
C3
L1
FIGURE 1B. CRYSTAL OSCILLATOR INTERFACE (3RD OVERTONE)
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REV. A JANUARY 20, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS83905
LOW SKEW, 1:6 CRYSTAL INTERFACE-TOLVCMOS / LVTTL FANOUT BUFFER RELIABILITY INFORMATION
TABLE 6A. JAVS. AIR FLOW TABLE
FOR
16 LEAD SOIC
JA by Velocity (Meters per Second)
0
Multi-Layer PCB, JEDEC Standard Test Boards 78.8C/W
1
71.1C/W
2
66.2C/W
TABLE 6B. JAVS. AIR FLOW TABLE
FOR
16 LEAD TSSOP
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 137.1C/W 89.0C/W
200
118.2C/W 81.8C/W
500
106.8C/W 78.1C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TABLE 6C.
JAVS. AIR FLOW TABLE FOR 20 LEAD VFQFN
JA by Velocity (Meters per Second)
0 1
126C/W 35C/W
2.5
116.9C/W 33.4C/W
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards
141.7C/W 38.5C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS83905 is: 339
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REV. A JANUARY 20, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS83905
LOW SKEW, 1:6 CRYSTAL INTERFACE-TOLVCMOS / LVTTL FANOUT BUFFER
16 LEAD SOIC PACKAGE OUTLINE - G SUFFIX
FOR
PACKAGE OUTLINE - M SUFFIX
FOR
16 LEAD TSSOP
TABLE 7A. PACKAGE DIMENSIONS
SYMBOL N A A1 B C D E e H h L 5.80 0.25 0.40 1.35 0.10 0.33 0.19 9.80 3.80 MINIMUM
FOR
16 LEAD SOIC
MAXIMUM
TABLE 7B. PACKAGE DIMENSIONS
SYMBOL N Minimum
FOR
TSSOP
Maximum
Millimeters
Millimeters
16 1.75 0.25 0.51 0.25 10.00 4.00 1.27 BASIC 6.20 0.50 1.27
16 -0.05 0.80 0.19 0.09 4.90 6.40 BASIC 4.30 0.65 BASIC 0.45 0 -0.75 8 0.10 4.50 1.20 0.15 1.05 0.30 0.20 5.10
A A1 A2 b c D E E1 e L aaa
0 8 Reference Document: JEDEC Publication 95, MS-012
Reference Document: JEDEC Publication 95, MO-153
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REV. A JANUARY 20, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS83905
LOW SKEW, 1:6 CRYSTAL INTERFACE-TOLVCMOS / LVTTL FANOUT BUFFER
20 LEAD VFQFN
PACKAGE OUTLINE - K SUFFIX
FOR
TABLE 7C. PACKAGE DIMENSIONS
FOR
20 LEAD VFQFN
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS SYMBOL N A A1 A3 b e ND NE D D2 E E2 L 0.75 0.35 0.75 4.0 2.80 0.75 0.18 0.50 BASIC 5 5 4.0 2.80 0.80 0 0.25 Reference 0.30 MINIMUM 20 1.0 0.05 MAXIMUM
Reference Document: JEDEC Publication 95, MO-220
83905AM
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REV. A JANUARY 20, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS83905
LOW SKEW, 1:6 CRYSTAL INTERFACE-TOLVCMOS / LVTTL FANOUT BUFFER
Marking 83905AM 83905AM 83905AML 83905AML TBD TBD 83905A 83905A Package 16 Lead SOIC 16 Lead SOIC 16 Lead "Lead-Free" SOIC 16 Lead "Lead-Free" SOIC 16 Lead TSSOP 16 Lead TSSOP 20 Lead VFQFN 20 Lead VFQFN Shipping Packaging tube 2500 tape & reel tube 2500 tape & reel tube 2500 tape & reel tube 2500 tape & reel Temperature 0C to 70C 0C to 70C 0C to 70C 0C to 70C 0C to 70C 0C to 70C 0C to 70C 0C to 70C
TABLE 8. ORDERING INFORMATION
Part/Order Number ICS83905AM ICS83905AMT ICS83905AMLF ICS83905AMLFT ICS83905AG ICS83905AGT ICS83905AK ICS83905AKT
The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 83905AM
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REV. A JANUARY 20, 2005

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